In telecommunications switches and other digital systems, considerable delay and power is also consumed moving high-bandwidth signals across chips. In conventional CMOS chips, such signals are driven at CMOS levels where the two power supplies are used to represent logic xe2x80x9c1xe2x80x9d and logic xe2x80x9c0xe2x80x9d. Consider moving a high-bandwidth STS-192 (10 Gb/s) signal across a long on-chip bus where the supply voltage is 1.8V and each signal line has 1 pF of capacitance. Using conventional CMOS signaling, not only is such system very slow, due to the large RC time constant of the long wire, but it also dissipates over 30 mW of power just transporting the signal.
Some prior art systems, such as that presented in Dally and Poulton, Digital Systems Engineering, Cambridge University Press, 1998, pp. 385-387, reduces the delay and power dissipation of on-chip signaling paths by employing differential signaling with a low-voltage swing using a precharged signaling arrangement. However, while such systems reduce power by lowering the voltage swing, they also consume additional power to precharge the lines each cycle. Also, this precharge operation limits the maximum rate at which the lines can operate.
In accordance with one aspect of the invention, a data link on an integrated circuit comprises a push-pull driver circuit, clocked from a clock, driving a pair of differential lines, one line driven high while the other line is pulled low. A receiver includes a sense amplifier clocked from the same clock.
Each line may be driven through a low swing with the driver circuit clocked through a timing circuit. The timing circuit includes a delay, the timing of which varies in a manner similar to timing variations in the driver circuit. Line-to-line coupling of the differential lines allows precharge of the lines without drawing precharge power.
The driver circuit may be an NMOS H-bridge. Both the driver and receiver may be formed of MOSFETs.
In accordance with another aspect of the invention, the on-chip transmission system includes a regenerative repeater, clocked from the clock, to regenerate the signal from the driver circuit. The repeater includes a sense amplifier, the output of which may enable the driver circuit of the repeater.